Recently, in order to increase the density of DRAM cells, there is used a bidirectional shared sense amplifier in which two or more bit line pairs are connected to a single sense amplifier.
In this bidirectional shared sense amplifier, n (n indicates an integer having a value of two or more) bit line pairs are connected to a single sense amplifier, in such a manner that the bit lines can be connected and disconnected to and from the sense amplifier through bit line selecting switches.
In this structure, a plurality of bit lines shares a single sense amplifier, and therefore, the number of the sense amplifier is reduced, with the result that the area of the chip is reduced.
FIG. 1 is a block diagram showing the constitution of such a bidirectional shared sense amplifier.
A DRAM cell array 10-1 includes a plurality of bit lines connected to a plurality of cells, and the bit lines (for example BL and/BL) are connected through a bit line equalizer section 11-1 and a bit line selecting switch section 12-1 to a sense amplifier 13.
On the other side of the sense amplifier 13, there are also connected bit lines (which are connected to a plurality of cells of a DRAM cell array 10-2) through a bit line equalizer section 11-2 and a bit line selecting switch section 12-2.
Further, a data input/output section 14 is connected to the sense amplifier 13, so that the data read by the sense amplifier would be transmitted to a data bus.
The bit line selecting switch receives bit line selecting signals BS0 and BS1 which are generated by a bit line selection signal generating section 15.
The first bit line selecting switch section 12-1 receives a bit line selecting signal BS0 from the bit line selection signal generating section 15, while the second bit line selecting switch section 12-2 receives a bit line selecting signal BS1 from the bit line selection signal generating section 15.
The bit line equalizer section receives bit line equalizing signals, and the first bit line equalizer section receives a bit line equalizing signal BLEQ0, while the second bit line equalizer 11-2 receives a bit line equalizing signal BLEQ1.
The bit line selecting signals BS0 and BS1 perform the function of selecting the respective bit lines, and the sense amplifier 13 senses the potential difference between the bit lines to amplify the difference. The bit line equalizer section performs the function of equalizing and releasing the bit lines. That is, before selecting the word line, the equalization of the bit lines is released by means of BLEQ0 and BLEQ1.
The data input/output section 14 serves as a path when reading or writing data.
The bit line selection signal generating section 15 controls the respective bit line selecting signals during a power up, during a bit line selection, and during a pre-charging.
FIG. 2 illustrates wave patterns showing the operation examples of the conventional bit line selecting circuit. In this drawing, an example is taken in which the signals BS0 and BS1 are selected by once respectively, and the illustration is made for the two cases of a bit line selection and a pre-charging.
During the time of pre-charging, all the signals are maintained at a Vcc level regardless of the preceding state of the bit line selecting signal.
Then during the selection of a bit line, the case of selecting the signal BS0 will be taken as an example. The selected signal BS0 is stepped up from the Vcc level to a Vpp level, and the bit line which corresponds to it is connected to the sense amplifier. The Vpp voltage is higher than the Vcc voltage as much as Vth of the switching transistor.
Meanwhile, the signal BS1 has not been selected, and therefore, it is shifted from Vcc to Vss.
Meanwhile, during the pre-charging, the signals BS0 and BS1 all have the Vcc level. This is due to the fact that, in order to equalize the bit lines, the potentials of the equalized bit lines have to be transmitted to the sense amplifier.
In this way, during the selection of a bit line, the signals corresponding to the selected bit lines are shifted to the Vpp level, while the rest of them are maintained at the Vss level. On the other hand, during the pre-charging, all the signals have the vcc level, thereby equalizing the sense amplifier.
During the selection, the equalizer signals BLEQ are shifted to a low level by the bit line equalizer section after being slightly delayed behind the signal /RAS. Thus the bit lines BL and /BL are stopped from being equalized, so that the bit lines would be isolated from a pre-charging voltage VBL.
Under this condition, the bit line selecting signal comes to have the Vpp level which is higher than Vcc+Vth, so that the bit line selecting switch consisting of an NMOS transistor TR would be able to connect the bit line to the sense amplifier without voltage loss.
Thereafter, if a word line to be selected is shifted to a high level by receiving a row address, then the charge of the cell which is connected to one of the bit lines BL and/BL is charge-distributed so as to have a slight high or slightly low voltage.
Under this condition, an enable signal is supplied to the sense amplifier, so that the voltage difference between the bit lines would be spread to Vcc and Vss. Ultimately, the data which is stored in the cell is transmitted to the bit line to be sent through the sense amplifier to the input/output line.
FIG. 3 is a block diagram showing the constitution of a double shared sense amplifier in which four pairs of bit lines are connected to a single sense amplifier.
In this structure, the number of the bit lines is twice, compared with that of FIG. 1.
DRAM cell arrays 20-1 and 20-2 include a plurality of bit lines which are connected to a plurality of cells. These bit lines (e.g., BL and /BL) are connected through a bit line equalizer section 21-1 and a bit line selecting switch sections 22-1 and 22-2 to a sense amplifier 23.
On the other side of the sense amplifier 23, there are connected bit lines which are connected to a plurality of cells of other DRAM cell arrays 20-3 and 20-4, the bit lines being connected through a bit line equalizer section 21-2 and bit line selection switch sections 22-3 and 22-4.
Further, a data input/output section 24 is connected to the sense amplifier 23, so that the data read out by the sense amplifier 23 can be transmitted to a data bus.
The bit line selecting switch receives bit line selecting signals BSU0, BSU1, BSD0 and BSD1 which are generated by a bit line selection signal generating section 25.
In this case, the signals BSU0, BSU1, BSD0 and BSD1 plays the role of selecting the bit lines, while signals BLEQU1, BLEQU0, BLEQD0 and BLEQD1 plays the roles of equalizing and releasing the bit lines.
An upper first bit line selecting switch section 22-1 receives bit line selecting signals BSU0 which are generated by the bit line selection signal generating section 25. A lower first bit line selecting switch section 22-2 receives bit line selecting signals BSU1, and an upper second bit line selecting switch section 22-3 receives bit line selecting signals BSD0, while a lower second bit line selecting switch section 22-4 receives bit line selecting signals BSD1.
Meanwhile, the bit line equalizer section receives bit line equalizing signals. A first bit line equalizer section 21-1 receives the bit line equalizing signals BLEQU0 for equalizing the bit lines which are connected to the upper first bit line selecting switch section. The first bit line equalizer section 21-1 also receives the bit line equalizing signals BLEQU1 for equalizing the bit lines which are connected to the lower first bit line selecting switch section.
The second bit line equalizer section 21-2 receives the bit line equalizing signals BLEQD0 for equalizing the bit lines which are connected to the second bit line selecting switch section. The second bit line equalizer section 21-2 also receives the bit line equalizing signals BLEQD1 for equalizing the bit lines which are connected to the lower bit line selecting switch section.
The bit line selecting signals, the sense amplifier 23, the bit line selection signal generating section 25 and the data input/output section 24 play the same roles as those of FIG. 1.
In this example like that of FIG. 2, the selection of the signals BSU0 and BSU1 respectively by once will be described.
First, during a pre-charging, the two signals all are maintained at the Vcc level regardless of the state of the preceding bit line selecting signal.
Then, during the selection of the bit line, in the case where the signal BSU0 is selected, the selected signal BSU0 is shifted from the Vcc to the Vpp so as to connect the relevant bit line to the sense amplifier. On the other hand, if the signal BSU1 has not been selected, it is shifted from the Vcc to the Vss.
During the next pre-charging, the signals BSU0 and BSU1 all are maintained at the Vcc level.
Thus, during the selection of bit lines, the signals corresponding to the selected bit lines are shifted to the Vpp level, and the rest of the signals are maintained at the Vss level. On the other hand, during the pre-charging, all the signals are maintained at the Vcc level so as to equalize the sense amplifier. The other operations are same as those of the example of FIG. 1.
FIG. 4 illustrates a conventional bit line selection signal generating circuit (15 and 25), and FIG. 5 illustrates a bit line selection signal generating section having two bit line selection signal generating circuits (15 and 25).
As shown in FIG. 4, the conventional bit line selection signal generating circuit (called BSG) for generating the signal BS0 is constituted such that a parallel circuit consisting of two NMOS transistors MN2 and MN3 is connected to a serial circuit consisting of one NMOS transistor MN1 and two PMOS transistors MP1 and MP2 connected to the Vcc level, the parallel circuit being connected to the Vss level. Further, a PMOS transistor MP3 which is connected to the Vpp source is connected to the connecting point between the transistors MN1 and MN2.
In order to generate bit line signals BS#, the gates of the PMOS transistor MP1 and the NMOS transistor MN2 are connected to a signal BSSUM#, and the gates of the PMOS transistor MP2 and the NMOS transistor MN3 are connected to a signal SRSUM#, while the gates of the NMOS transistor MN1 and the PMOS transistor MP3 are connected to n300. The output signal BS# is connected to the connection point between the transistors MP3 and MN3.
In order for the BSG to generate bit line signals BS0, the gates of the PMOS transistor MP1 and the NMOS transistor MN2 are connected to a signal BSSUM0, and the gates of the PMOS transistor MP2 and the NMOS transistor MN4 are connected to a signal SRSUM0, while the gates of the NMOS transistor MN1 and the PMOS transistor MP3 are connected to n300. The output signal BS0 is connected to the connection point between the transistor MP3 and the transistor MN3. The bit line signal generating section is called BSG0, and its operation is as shown in Table 1.
During the pre-charging, the signals BSSUM0 and BRSUM0 have a value of "0", and n300 has a value of "1" , so that the circuit output BS0 would have the Vcc level. "1" indicates a high level, and "0" indicates a low level. During the pre-charging, when the signals BSSUM0 and BRSUM0 are "0" and n300 is "1", the transistors MP1, MP2 and MN1 are turned on, and the transistors MP3, MN2 and MN3 are turned off, with the result that the output BS0 of this circuit comes to have the Vcc level.
When the BS0 is selected, the signals BSSUM0 and BRSUM0 becomes "0", and n300 also becomes "0", with the result that the transistor MP3 is turned on, and that the transistor MN1 is turned off. Consequently, the output BS0 of this circuit comes to have the Vpp level.
When the pre-charging is carried out at the next time, the signals BSSUM0 and BRSUM0 becomes "0", and n300 becomes "1", with the result that the output BS0 of this circuit becomes the Vss level.
Then the constitution of the bit line selection signal generating circuit BSG1 which is for generating a signal BS1 is same as that of the circuit BSG0, except that the input signal is connected to BSSUM1 instead of BSSUM0, to BRSUM1 instead of BRSUM0, and to n301 instead of n300. The output signal BS1 is connected to the connection point between the transistors MP3 and MN3.
The operation of the bit line selection signal generating section thus connected is as shown in the right portion of Table 1.
That is, during the pre-charging, the signals BSSUM1 and BRSUM1 become "0", and n300 becomes "1", with the result that the output BS1 of this circuit has the Vcc level.
When the BS0 is selected, the signals BSSUM1 and BRSUM1 becomes "1", and n301 also becomes "1", with the result that the output BS1 of this circuit has the Vss level.
When the pre-charging is carried out again next time, the signals BSSUM1 and BRSUM1 becomes "0" and n301 becomes "1" with the result that the output BS1 of this circuit has the Vcc level.
When the BS1 is selected next time, the signals BSSUM1 and BRSUM1 becomes "0", and n301 also becomes "0", with the result that the output BS1 of this circuit has the Vpp level.
The bit line selection signal generating section 25 of FIG. 3 includes four bit line selection signal generating circuits of FIG. 4, and these four circuits receive respectively different input signals.
When the output signals BSU0, BSU1, BSD0 and BSD1 are selected, only these signals are shifted to the Vpp level, while during the pre-charging, they come to have the Vcc level. Meanwhile, when other signals are selected, they come to have the Vss level.
In the conventional technique described above, during both the power up and the pre-charging, all the selected signals are maintained at the Vcc level. Therefore, as can be seen in FIG. 2, in accordance with the selections of the respective bit lines, signal transitions in the form of Vcc.fwdarw.Vss and Vss.fwdarw.Vcc occur many times, with the result that the power consumption is increased. Consequently, it is unsuitable for forming a low power consumption DRAM.